Rambus PCIe 5.0 Digital Controller Features


Rambus’ PCIe 5.0 IP core for FPGAs is a system IP block that uses high bandwidth memory. It has been validated to run within FPGA fabric, enabling PCIe 5.0 performance at 32 GT/s in FPGAs with a soft controller.

The IP core delivers the full-privileged cycle integrity at 32 GB/s required for demanding multi-lane bridging applications in enterprise data centers, consumer electronics, and military systems. 

The PCIe 5.0 IP core is backward compatible with PCIe 4.0 and delivers a smooth upgrade path for applications requiring 32 GT/s or more performance.

PCIe 5.0 Technology

The PCIe 5.0 technology derives from the acquisition of PLDA by Rambus in December 2015. This acquisition expanded the Rambus interface portfolio and brought together critical capabilities from both companies. That’s including controller design, high-speed memory and test, and measurement expertise. 

The PLDA team developed the PCIe 5.0 IP core before the acquisition.

“We are excited to see this leading PCIe 5.0 IP core come to market,” said Bill Bauknight, chief executive officer at PLDA. “The IP core demonstrates the strength of the PLDA team and positions Rambus to bring innovative solutions to the marketplace.”

This development is part of Rambus’ continuing growth of its interface portfolio with critical interface technologies for communications.

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These new and unique interfaces help customers solve specific problems and enhance the overall user experience by enabling more efficient and practical resources.

Rambus’ PCIe 5.0 IP core for FPGAs is scheduled for general availability in Q4 2017. Rambus’ PCIe 4.0 IP cores are available now, providing comprehensive PCIe Gen 4 solutions to customers. Developing applications with high-end FPGAs such as the Xilinx UltraScale+™ FPGA family.

Features Of The Rambus PCIe 5.0 Digital Controller

  • The PCIe 5.0 digital controller implements a new high bandwidth memory architecture with a 1:1 mapping to the FPGA, enabling data rates up to 32GT/s. 
  • It includes a set of features that reduce the risk of realizing the best performance from the FPGA by monitoring, maintaining, and repairing VCC across all PCIe lanes, even in multi-lane configurations. It is protocol-aware and can support all PCIe features, including CPLD configuration.
  • The PCIe 5.0 digital controller implements a programmable scheduling network that supports custom and weighted round-robin allocation of end-point and other resources to virtual functions. 
  • The flexible design supports both forwarding and non-forwarding packets and multiple switch/bridge users per cycle.
  • The feature set is based on the latest PCIe 5.0 specification. The controller designs to transition to future advances in this technology.
  • The PCIe 5.0 digital controller supports per-lane or multi-lane bridging applications, with or without SRIOV capability. Using the same programming model and configuration parameters at 32GT/s per lane or 128GT/s per PF.

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